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ATS
2002
IEEE
136views Hardware» more  ATS 2002»
15 years 11 months ago
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
IPPS
1997
IEEE
15 years 10 months ago
A Randomized Sorting Algorithm on the BSP model
We present a new randomized sorting algorithm on the Bulk-SynchronousParallel (BSP) model. The algorithm improves upon the parallel slack of previous algorithms to achieve optimal...
Alexandros V. Gerbessiotis, Constantinos J. Siniol...
176
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ASAP
1995
IEEE
145views Hardware» more  ASAP 1995»
15 years 10 months ago
An array processor for inner product computations using a Fermat number ALU
This paper explores an architecture for parallel independent computations of inner products over the direct product ring . The structure is based on the polynomial mapping of the ...
Wenzhe Luo, Graham A. Jullien, Neil M. Wigley, Wil...
COLING
2008
15 years 8 months ago
The Choice of Features for Classification of Verbs in Biomedical Texts
We conduct large-scale experiments to investigate optimal features for classification of verbs in biomedical texts. We introduce a range of feature sets and associated extraction ...
Anna Korhonen, Yuval Krymolowski, Nigel Collier
DICTA
2003
15 years 8 months ago
Epipole Estimation under Pure Camera Translation
 The position of the epipole (or focus of expansion), when a camera  moves  under  pure  translation,  provides  useful  information  in  a  range  of  comp...
Zezhi Chen, Nick Pears, John McDermid, Thomas Hese...