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DATE
2009
IEEE
120views Hardware» more  DATE 2009»
16 years 20 days ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
DSN
2007
IEEE
16 years 7 days ago
Minimizing Response Time for Quorum-System Protocols over Wide-Area Networks
A quorum system is a collection of sets (quorums) of servers, where any two quorums intersect. Quorumbased protocols underly modern edge-computing architectures and throughput-sca...
Florian Oprea, Michael K. Reiter
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
15 years 10 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
DAC
2004
ACM
15 years 9 months ago
On test generation for transition faults with minimized peak power dissipation
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
FPL
2008
Springer
104views Hardware» more  FPL 2008»
15 years 7 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...