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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
ADHOCNOW
2009
Springer
16 years 21 days ago
Auction Aggregation Protocols for Wireless Robot-Robot Coordination
Abstract. Robots coordinate among themselves to select one of them to respond to an event reported to one of robots. The goal is to minimize the communication cost of selecting bes...
Ivan Mezei, Veljko Malbasa, Ivan Stojmenovic
ESA
2009
Springer
124views Algorithms» more  ESA 2009»
16 years 19 days ago
Minimum Makespan Multi-vehicle Dial-a-Ride
Dial-a-Ride problems consist of a set V of n vertices in a metric space (denoting travel time between vertices) and a set of m objects represented as source-destination pairs {(si,...
Inge Li Gørtz, Viswanath Nagarajan, R. Ravi
154
Voted
CODES
2008
IEEE
16 years 16 days ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
ICYCS
2008
IEEE
16 years 15 days ago
FAST CASH: FAir and STable Channel ASsignment on Heterogeneous Wireless Mesh Network
— Nowadays wireless mesh routers are facilitating with more wireless channels than ever because of the advanced wireless communication technologies such as OFDM, SDR and CR(cogni...
Panlong Yang, Guihai Chen