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ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
16 years 4 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
ICCAD
2005
IEEE
105views Hardware» more  ICCAD 2005»
16 years 4 months ago
Weighted control scheduling
Abstract — This paper describes a practical technique for the optimal scheduling of control dominated systems minimizing the weighted average latency over all control branches. S...
Aravind Vijayakumar, Forrest Brewer
DATE
2005
IEEE
100views Hardware» more  DATE 2005»
16 years 25 days ago
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a ...
G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, F...
EVOW
2004
Springer
16 years 18 days ago
A Scenario-Based Approach to Protocol Design Using Evolutionary Techniques
An evolutionary approach to design communication protocols from scenario-based specifications is presented. It enables to automatically generate finite-state models of protocol ent...
Sérgio G. Araújo, Antônio C. M...
ISAAC
2003
Springer
97views Algorithms» more  ISAAC 2003»
16 years 12 days ago
Equilibria for Networks with Malicious Users
We consider the problem of characterizing user equilibria and optimal solutions for selfish routing in a given network. We extend the known models by considering malicious behavio...
George Karakostas, Anastasios Viglas