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DAC
1997
ACM
15 years 11 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 10 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
15 years 8 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
ER
2008
Springer
134views Database» more  ER 2008»
15 years 8 months ago
On Measuring Process Model Similarity Based on High-Level Change Operations
For various applications there is the need to compare the similarity between two process models. For example, given the as-is and to-be models of a particular business process, we ...
Chen Li, Manfred Reichert, Andreas Wombacher
172
Voted
JAIR
2008
123views more  JAIR 2008»
15 years 6 months ago
CTL Model Update for System Modifications
Model checking is a promising technology, which has been applied for verification of many hardware and software systems. In this paper, we introduce the concept of model update to...
Yan Zhang, Yulin Ding