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ADC
1999
Springer
97views Database» more  ADC 1999»
15 years 11 months ago
Pseudo-Naive Evaluation
We introduce pseudo-naive evaluation, a method for execution of mixed top-down/bottom-up logic programs and deductive databases. The method is intermediate in power between naive ...
Donald A. Smith, Mark Utting
DAC
2007
ACM
16 years 8 months ago
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 3 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
16 years 1 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
AGILE
2007
Springer
127views GIS» more  AGILE 2007»
16 years 1 months ago
Space-contained conflict revision, for geographic information
Using qualitative reasoning with geographic information, contrarily, for instance, with robotics, looks not only fastidious (i.e.: encoding knowledge Propositional Logics PL), but ...
Omar Doukari, Robert Jeansoulin