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CORR
2010
Springer
122views Education» more  CORR 2010»
15 years 7 months ago
Facility Location with Client Latencies: Linear-Programming based Techniques for Minimum-Latency Problems
We introduce a problem that is a common generalization of the uncapacitated facility location (UFL) and minimum latency (ML) problems, where facilities not only need to be opened ...
Deeparnab Chakrabarty, Chaitanya Swamy
ISMVL
2008
IEEE
160views Hardware» more  ISMVL 2008»
16 years 1 months ago
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean Sati...
Daniel Große, Robert Wille, Gerhard W. Dueck...
IPPS
2007
IEEE
16 years 1 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
RTSS
1997
IEEE
15 years 11 months ago
On-the-fly symbolic model checking for real-time systems
This paper presents an on-the-fly and symbolic algorithm for checking whether a timed automaton satisfies a formula of a timed temporal logic which is more expressive than TCTL....
Ahmed Bouajjani, Stavros Tripakis, Sergio Yovine
ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
15 years 11 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu