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CONCUR
2006
Springer
15 years 8 months ago
Model Checking Quantified Computation Tree Logic
Propositional temporal logic is not suitable for expressing properties on the evolution of dynamically allocated entities over time. In particular, it is not possible to trace such...
Arend Rensink
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
15 years 11 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
ICCAD
1998
IEEE
153views Hardware» more  ICCAD 1998»
15 years 11 months ago
Intellectual property protection by watermarking combinational logic synthesis solutions
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak,...
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
15 years 10 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
DIAGRAMS
2008
Springer
15 years 8 months ago
Diagrammatic Logic of Existential Graphs: A Case Study of Commands
Diagrammatic logics have advantages over symbolic cousins. Peirce thought that logical diagrams (Existential Graphs, EG) are capable of "expression of all assertions", as...
Ahti-Veikko Pietarinen