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DFT
2005
IEEE
92views VLSI» more  DFT 2005»
16 years 14 days ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
16 years 14 days ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
ARCS
2005
Springer
16 years 12 days ago
Self-Organization in Sensor Networks using Bio-Inspired Mechanisms
Bio-inspired communication methodologies promise to enable more scalable self-organizing network infrastructures. Especially in the area of mobile ad hoc sensor networks, such sol...
Falko Dressler, Bettina Krüger, Gerhard Fuchs...
VLSI
2005
Springer
16 years 9 days ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
WER
2005
Springer
16 years 9 days ago
Using Task Descriptions for the Specification of Web Application Requirements
There are a significant number of proposals for modelling and developing Web Applications, but very few of them state rigorously how to elicit and represent requirements, and how t...
Pedro Valderas, Joan Fons, Vicente Pelechano