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DATE
2006
IEEE
83views Hardware» more  DATE 2006»
16 years 28 days ago
What lies between design intent coverage and model checking?
Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that ca...
Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. ...
PAM
2005
Springer
16 years 10 days ago
Using Simple Per-Hop Capacity Metrics to Discover Link Layer Network Topology
At present, link layer topology discovery methodologies rely on protocols that are not universally available, such as SNMP. Such methodologies can only be applied to a subset of al...
Shane Alcock, Anthony McGregor, Richard Nelson
161
Voted
EDOC
2002
IEEE
15 years 11 months ago
An MDA-Based Model for Vertical Application Task Forces: An Experience Report
Thispaper describes a set of modeling techniquesfor developing vertical applications in specific domains. Previous approaches are mainly focused on obtaining final applications. W...
Luis E. Anido-Rifón, Juan M. Santos, Judith...
176
Voted
ICCVW
1999
Springer
15 years 11 months ago
An Experimental Comparison of Stereo Algorithms
While many algorithms for computing stereo correspondence have been proposed, there has been very little work on experimentally evaluating algorithm performance, especially using r...
Richard Szeliski, Ramin Zabih
176
Voted
DAC
1997
ACM
15 years 11 months ago
Quadratic Placement Revisited
The “quadratic placement” methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array desi...
Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huan...