Sciweavers

2078 search results - page 96 / 416
» MetaCores: Design and Optimization Techniques
Sort
View
ISQED
2003
IEEE
121views Hardware» more  ISQED 2003»
15 years 11 months ago
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization
— The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristic...
Volkan Kursun, Siva Narendra, Vivek De, Eby G. Fri...
DAC
2005
ACM
15 years 8 months ago
Template-driven parasitic-aware optimization of analog integrated circuit layouts
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 7 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
TCAD
2008
92views more  TCAD 2008»
15 years 5 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
JSAC
2008
111views more  JSAC 2008»
15 years 6 months ago
The end-to-end rate control in multiple-hop wireless networks: Cross-layer formulation and optimal allocation
In this paper, we study the theoretical problem of the end-to-end rate assignment for multi-hop wireless networks. Specifically, we consider the problem of joint congestion control...
Chengnian Long, Bo Li, Qian Zhang, Bin Zhao, Bo Ya...