2078 search results - page 208 / 416 » MetaCores: Design and Optimization Techniques |
147
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ISQED
2006
IEEE
16 years 18 days ago
2006
IEEE
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
175
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ASPLOS
2008
ACM
15 years 8 months ago
2008
ACM
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these opti...
156
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ECBS
2006
IEEE
16 years 19 days ago
2006
IEEE
For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system l...
163
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
174
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CEC
2005
IEEE
16 years 6 days ago
2005
IEEE
An Internet Java Applet http://www.cs.essex.ac.uk/staff/poli/ SoloPong/ allows users anywhere to play the Solo Pong game. We compare people’s performance to a hand coded “Optim...