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LCTRTS
2010
Springer
16 years 1 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
TSMC
2011
324views more  TSMC 2011»
15 years 1 months ago
Genetic Algorithms With Guided and Local Search Strategies for University Course Timetabling
—The university course timetabling problem (UCTP) is a combinatorial optimization problem, in which a set of events has to be scheduled into time slots and located into suitable ...
Shengxiang Yang, Sadaf Naseem Jat
TCAD
2002
99views more  TCAD 2002»
15 years 6 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra
DAC
1999
ACM
16 years 7 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes
AAMAS
2010
Springer
15 years 6 months ago
Evolutionary mechanism design: a review
Abstract The advent of large-scale distributed systems poses unique engineering challenges. In open systems such as the internet it is not possible to prescribe the behaviour of al...
Steve Phelps, Peter McBurney, Simon Parsons