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» MetaCores: Design and Optimization Techniques
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DATE
2007
IEEE
109views Hardware» more  DATE 2007»
16 years 23 days ago
Area optimization of multi-cycle operators in high-level synthesis
Conventional high-level synthesis algorithms usually employ multi-cycle operators to reduce the cycle length in order to improve the circuit performance. These operators need seve...
María C. Molina, Rafael Ruiz-Sautua, Jose M...
INFOCOM
2006
IEEE
16 years 13 days ago
Optimal Scheduling Algorithms for Input-Queued Switches
— The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high line speeds. A central problem in designing an input-queued swit...
Devavrat Shah, Damon Wischik
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
16 years 1 days ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ECEASST
2006
96views more  ECEASST 2006»
15 years 6 months ago
Optimizing Pattern Matching Compilation by Program Transformation
Motivated by the promotion of rewriting techniques and their use in major industrial applications, we have designed Tom: a pattern matching layer on top of conventional programming...
Emilie Balland, Pierre-Etienne Moreau
ISQED
2009
IEEE
112views Hardware» more  ISQED 2009»
16 years 1 months ago
Estimation and optimization of reliability of noisy digital circuits
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
Satish Sivaswamy, Kia Bazargan, Marc D. Riedel