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DAC
2005
ACM
16 years 7 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...
CORR
2007
Springer
117views Education» more  CORR 2007»
15 years 6 months ago
Sensor Networks with Random Links: Topology Design for Distributed Consensus
—In a sensor network, in practice, the communication among sensors is subject to: 1) errors that can cause failures of links among sensors at random times; 2) costs; and 3) const...
Soummya Kar, José M. F. Moura
ICCAD
2004
IEEE
124views Hardware» more  ICCAD 2004»
16 years 3 months ago
Architectural-level synthesis of digital microfluidics-based biochips
Microfluidics-based biochips offer a promising platform for massively parallel DNA analysis, automated drug discovery, and real-time biomolecular recognition. Current techniques f...
Fei Su, Krishnendu Chakrabarty
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
16 years 1 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...
ICMCS
2000
IEEE
91views Multimedia» more  ICMCS 2000»
15 years 10 months ago
Streaming Video with Optimized Reconstruction-Based DCT
One fundamental problem with streaming video data over unreliable IP networks is that packets may be dropped or arrive too late for real-time playback. Traditional error-control s...
Xiao Su, Benjamin W. Wah