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ERSA
2008
185views Hardware» more  ERSA 2008»
15 years 8 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
PROLAMAT
1998
15 years 8 months ago
Design Knowledge Collection by Modeling
Since design is a process in which designers use various kinds of knowledge and it is an open-ended problem, it is difficult to prepare all necessary knowledge before design. Also...
Masaharu Yoshioka, T. Sekiya, Tetsuo Tomiyama
DAC
2008
ACM
16 years 7 months ago
Predictive design space exploration using genetically programmed response surfaces
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surface...
Henry Cook, Kevin Skadron
DAC
2007
ACM
16 years 7 months ago
Parameterized Macromodeling for Analog System-Level Design Exploration
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
Jian Wang, Xin Li, Lawrence T. Pileggi
CHI
2010
ACM
16 years 1 months ago
Artifacts in design: representation, ideation, and process
Artifacts—representations that express properties or captured information—can serve to inspire, represent, and manage the decisions made throughout the design process. This wo...
D. Scott McCrickard, Michael E. Atwood, Gayle Curt...
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