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» Memory modeling for system synthesis
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OOPSLA
2010
Springer
15 years 4 months ago
Hera-JVM: a runtime system for heterogeneous multi-core architectures
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
Ross McIlroy, Joe Sventek
CASES
2001
ACM
15 years 10 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen
CASES
2004
ACM
15 years 11 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
ISORC
2005
IEEE
15 years 12 months ago
Object-Reuse for More Predictable Real-Time Java Behavior
One of the problems with Java for real-time systems is the unpredictable behavior of garbage collection (GC). GC introduces unexpected load and causes undesirable delays for real-...
Jameela Al-Jaroodi, Nader Mohamed
SSS
2009
Springer
15 years 10 months ago
An Optimal Self-stabilizing Firing Squad
Consider a fully connected network where up to t processes may crash, and all processes start in an arbitrary memory state. The self-stabilizing firing squad problem consists of e...
Danny Dolev, Ezra N. Hoch, Yoram Moses