With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Background: The Generalized Hidden Markov Model (GHMM) has proven a useful framework for the task of computational gene prediction in eukaryotic genomes, due to its flexibility an...
William H. Majoros, Mihaela Pertea, Arthur L. Delc...
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...
We propose a novel equalization method for doubly selective wireless channels, whose taps are represented by an arbitrary Basis Expansion Model (BEM). We view such a channel in the...
Tomasz Hrycak, Saptarshi Das, Gerald Matz, Hans G....