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FPL
2006
Springer
242views Hardware» more  FPL 2006»
15 years 10 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
ICS
2009
Tsinghua U.
16 years 1 months ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron
BMCBI
2005
87views more  BMCBI 2005»
15 years 6 months ago
Efficient decoding algorithms for generalized hidden Markov model gene finders
Background: The Generalized Hidden Markov Model (GHMM) has proven a useful framework for the task of computational gene prediction in eukaryotic genomes, due to its flexibility an...
William H. Majoros, Mihaela Pertea, Arthur L. Delc...
CGF
2010
105views more  CGF 2010»
15 years 6 months ago
Streaming-Enabled Parallel Dataflow Architecture for Multicore Systems
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...
TSP
2010
15 years 1 months ago
Low complexity equalization for doubly selective channels modeled by a basis expansion
We propose a novel equalization method for doubly selective wireless channels, whose taps are represented by an arbitrary Basis Expansion Model (BEM). We view such a channel in the...
Tomasz Hrycak, Saptarshi Das, Gerald Matz, Hans G....