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ICASSP
2008
IEEE
16 years 17 days ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
LCPC
2004
Springer
15 years 11 months ago
Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers
Abstract. This paper describes performance of OSCAR multigrain parallelizing compiler on various SMP servers, such as IBM pSeries 690, Sun Fire V880, Sun Ultra 80, NEC TX7/i6010 an...
Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako...
CODES
2005
IEEE
15 years 11 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
IEEEPACT
2009
IEEE
16 years 23 days ago
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures
Increasing demand for performance and efficiency has driven the computer industry toward multicore systems. These systems have become the industry standard in almost all segments...
Amir Hormati, Yoonseo Choi, Manjunath Kudlur, Rodr...
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
15 years 11 months ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...