Sciweavers

354 search results - page 31 / 71
» Memory and compiler optimizations for low-power and -energy
Sort
View
DAC
2009
ACM
15 years 10 months ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
SP
2008
IEEE
16 years 14 days ago
Preventing Memory Error Exploits with WIT
Attacks often exploit memory errors to gain control over the execution of vulnerable programs. These attacks remain a serious problem despite previous research on techniques to pr...
Periklis Akritidis, Cristian Cadar, Costin Raiciu,...
EUROPAR
2004
Springer
15 years 11 months ago
Exploiting Spatial Store Locality Through Permission Caching in Software DSMs
Abstract. Fine-grained software-based distributed shared memory (SWDSM) systems typically maintain coherence with in-line checking code at load and store operations to shared memor...
Håkan Zeffer, Zoran Radovic, Oskar Grenholm,...
234
Voted
SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
15 years 4 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker
LISP
2008
104views more  LISP 2008»
15 years 6 months ago
Flattening tuples in an SSA intermediate representation
For functional programs, unboxing aggregate data structures such as tuples removes memory indirections and frees dead components of the decoupled structures. To explore the consequ...
Lukasz Ziarek, Stephen Weeks, Suresh Jagannathan