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LCPC
2005
Springer
16 years 4 days ago
Scalable Array SSA and Array Data Flow Analysis
Static Single Assignment (SSA) has been widely accepted as the intermediate program representation of choice in most modern compilers. It allows for a much more efficient data flo...
Silvius Rus, Guobin He, Lawrence Rauchwerger
SC
2004
ACM
16 years 1 days ago
Big Wins with Small Application-Aware Caches
Large datasets, on the order of GB and TB, are increasingly common as abundant computational resources allow practitioners to collect, produce and store data at higher rates. As d...
Julio C. López, David R. O'Hallaron, Tianka...
ICPPW
2003
IEEE
15 years 12 months ago
A Dynamic Load Balancing Scheme for I/O-Intensive Applications in Distributed Systems
In this paper, a new I/O-aware load-balancing scheme is presented to improve overall performance of a distributed system with a general and practical workload including I/O activi...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
IEEEPACT
2002
IEEE
15 years 11 months ago
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
Jaewook Shin, Jacqueline Chame, Mary W. Hall
201
Voted
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 11 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor