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PPOPP
2010
ACM
16 years 3 months ago
Data transformations enabling loop vectorization on multithreaded data parallel architectures
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrig...
MEMOCODE
2008
IEEE
16 years 1 months ago
Estimating the Performance of Cache Replacement Policies
—Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system’...
Daniel Grund, Jan Reineke
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
16 years 1 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
CODES
2007
IEEE
16 years 29 days ago
A data protection unit for NoC-based architectures
Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
ISSAC
2007
Springer
107views Mathematics» more  ISSAC 2007»
16 years 23 days ago
A disk-based parallel implementation for direct condensation of large permutation modules
Through the use of a new disk-based method for enumerating very large orbits, condensation for orbits with tens of billions of elements can be performed. The algorithm is novel in...
Eric Robinson, Jürgen Müller 0004, Gene ...