3202 search results - page 369 / 641 » Memory access scheduling |
168
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CF
2004
ACM
16 years 2 days ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
200
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CSCW
2004
ACM
16 years 2 days ago
2004
ACM
The lack of lightweight communication channels and other technical and sociological difficulties make it hard for new members of a non-collocated software development team to lea...
195
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TC
2008
15 years 6 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
169
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TCAD
2008
15 years 6 months ago
2008
New fusion memory devices consisting of multiple heterogeneous memory components in a single die or package offer efficient ways to optimize embedded systems in terms of energy, pe...
198
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SIAMCOMP
1998
15 years 6 months ago
1998
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...