3202 search results - page 314 / 641 » Memory access scheduling |
162
click to vote
ICASSP
2011
IEEE
14 years 10 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
162
click to vote
DAC
2006
ACM
16 years 7 months ago
2006
ACM
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
120
click to vote
WWW
2003
ACM
16 years 7 months ago
2003
ACM
Since CDN simulations are known to be highly memory-intensive, in this paper, we argue the need for reducing the memory requirements of such simulations. We propose a novel memory...
186
Voted
ICCD
2005
IEEE
16 years 3 months ago
2005
IEEE
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
186
click to vote
ICS
2009
Tsinghua U.
16 years 1 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...