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TVLSI
2010
15 years 1 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
IACR
2011
110views more  IACR 2011»
14 years 6 months ago
On the (In)security of Hash-based Oblivious RAM and a New Balancing Scheme
With the gaining popularity of remote storage (e.g. in the Cloud), we consider the setting where a small, protected local machine wishes to access data on a large, untrusted remot...
Eyal Kushilevitz, Steve Lu, Rafail Ostrovsky
JSA
2007
191views more  JSA 2007»
15 years 6 months ago
Automated memory-aware application distribution for Multi-processor System-on-Chips
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
Heikki Orsila, Tero Kangas, Erno Salminen, Timo D....
DATE
2009
IEEE
176views Hardware» more  DATE 2009»
16 years 1 months ago
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Abstract— This paper presents a six-transistor (6T) singleended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-Î and low-power embedd...
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Sara...
CCGRID
2005
IEEE
16 years 8 days ago
A distributed shared buffer space for data-intensive applications
Efficient memory allocation and data transfer for cluster-based data-intensive applications is a difficult task. Both changes in cluster interconnects and application workloads ...
Renaud Lachaize, Jorgen S. Hansen