3202 search results - page 270 / 641 » Memory access scheduling |
149
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VLSISP
2008
15 years 6 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
187
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CF
2009
ACM
16 years 1 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
174
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FPL
2007
Springer
16 years 23 days ago
2007
Springer
The complexity of today’s embedded applications requires modern high-performance embedded System-on-Chip (SoC) platforms to be multiprocessor architectures. Advances in FPGA tec...
211
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IEEEPACT
2005
IEEE
16 years 6 days ago
2005
IEEE
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...
165
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SP
2003
IEEE
15 years 12 months ago
2003
IEEE
Language run-time systems are often called upon to safely execute mutually distrustful tasks within the same runtime, protecting them from other tasks’ bugs or otherwise hostile...