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IPPS
1998
IEEE
15 years 10 months ago
Scheduling with Communication Delays and Data Routing in Message Passing Architectures
This work deals with the scheduling problem of a directed acyclic graph with interprocessor communication delays. The objective is to minimize the makespan, taking into account the...
Aziz Moukrim, Alain Quilliot
FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
15 years 10 months ago
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassil...
TCC
2009
Springer
130views Cryptology» more  TCC 2009»
16 years 7 months ago
How Efficient Can Memory Checking Be?
We consider the problem of memory checking, where a user wants to maintain a large database on a remote server but has only limited local storage. The user wants to use the small ...
Cynthia Dwork, Moni Naor, Guy N. Rothblum, Vinod V...
HIPC
2007
Springer
16 years 22 days ago
Self-optimization of Performance-per-Watt for Interleaved Memory Systems
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...
Bithika Khargharia, Salim Hariri, Mazin S. Yousif
IPSN
2007
Springer
16 years 22 days ago
Harbor: software-based memory protection for sensor nodes
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
Ram Kumar, Eddie Kohler, Mani B. Srivastava