3202 search results - page 148 / 641 » Memory access scheduling |
167
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ISCAS
2006
IEEE
16 years 12 days ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
133
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ASPDAC
2006
ACM
16 years 11 days ago
2006
ACM
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
159
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
157
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
154
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BIRTHDAY
2009
Springer
15 years 11 months ago
2009
Springer
For many aspects of memory theoretical treatment already exists, in particular for: simple cache construction, store buers and store buer forwarding, cache coherence protocols, o...