Sciweavers

820 search results - page 52 / 164
» Memory System Connectivity Exploration
Sort
View
CHI
2008
ACM
16 years 6 months ago
Feasibility and pragmatics of classifying working memory load with an electroencephalograph
A reliable and unobtrusive measurement of working memory load could be used to evaluate the efficacy of interfaces and to provide real-time user-state information to adaptive syst...
David B. Grimes, Desney S. Tan, Scott E. Hudson, P...
FASE
2005
Springer
15 years 11 months ago
Checking Memory Safety with Blast
Abstract. Blast is an automatic verification tool for checking temporal safety properties of C programs. Given a C program and a temporal safety property, Blast statically proves ...
Dirk Beyer, Thomas A. Henzinger, Ranjit Jhala, Rup...
ASPLOS
2011
ACM
14 years 9 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
DAC
1999
ACM
16 years 7 months ago
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems
This paper presents a methodology for cycle-accurate simulation of energy dissipation in embedded systems. The ARM Ltd. 1 instruction-level cycle-accurate simulator is extended wi...
Tajana Simunic, Luca Benini, Giovanni De Micheli
IMS
2000
123views Hardware» more  IMS 2000»
15 years 9 months ago
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
Many architectural ideas that appear to be useful from a hardware standpoint fail to achieve wide acceptance due to lack of compiler support. In this paper we explore the design of...
David Judd, Katherine A. Yelick, Christoforos E. K...