87 search results - page 8 / 18 » Memory Management in a Combined VIA SCI Hardware |
159
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ISCA
2009
IEEE
16 years 19 days ago
2009
IEEE
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
203
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HPCA
2011
IEEE
14 years 9 months ago
2011
IEEE
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory...
183
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ISCA
1999
IEEE
15 years 10 months ago
1999
IEEE
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
199
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SOSP
2009
ACM
16 years 2 months ago
2009
ACM
Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memo...
146
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IPPS
2002
IEEE
15 years 11 months ago
2002
IEEE
Eclipse is a heterogeneous multiprocessor architecture for high-performance media processing, including highdefinition MPEG encoding/decoding. The scalable architecture framework ...