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IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 1 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ECRTS
2006
IEEE
16 years 28 days ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
CINQ
2004
Springer
225views Database» more  CINQ 2004»
16 years 8 days ago
A Data Mining Query Language for Knowledge Discovery in a Geographical Information System
Spatial data mining is a process used to discover interesting but not explicitly available, highly usable patterns embedded in both spatial and nonspatial data, which are possibly ...
Donato Malerba, Annalisa Appice, Michelangelo Ceci
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
16 years 5 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ICC
2007
IEEE
115views Communications» more  ICC 2007»
15 years 10 months ago
Super-Wideband SSN Suppression in High-Speed Digital Communication Systems by Using Multi-Via Electromagnetic Bandgap Structures
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
MuShui Zhang, YuShan Li, LiPing Li, Chen Jia