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MEMOCODE
2005
IEEE
16 years 1 days ago
Synthesis of synchronous assertions with guarded atomic actions
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyu...
IPPS
2002
IEEE
15 years 11 months ago
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit speci...
John O'Donnell
CEEMAS
2001
Springer
15 years 11 months ago
A Modelling Environment for Mind and Matter Aspects of Intentional Behaviour
In this paper the internal dynamics of mental states, in particular states based on beliefs, desires and intentions, is formalised using a temporal language. A software environment...
Catholijn M. Jonker, Jan Treur, Wouter C. A. Wijng...
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
15 years 11 months ago
A BIST Scheme for On-Chip ADC and DAC Testing
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
ICPP
2000
IEEE
15 years 11 months ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...