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ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
15 years 4 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
PERCOM
2010
ACM
15 years 1 months ago
The architecture design of a cross-domain context management system
A new context management framework, which supports the interaction between different domain context managers, is proposed. Two different context producerconsumer patterns are defin...
Bin Guo, Lin Sun, Daqing Zhang
HPCA
2012
IEEE
14 years 2 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
MOBISYS
2003
ACM
16 years 6 months ago
System Services for Ad-Hoc Routing: Architecture, Implementation and Experiences
This work explores several system issues regarding the design and implementation of routing protocols for ad-hoc wireless networks. We examine the routing architecture in current ...
Vikas Kawadia, Yongguang Zhang, Binita Gupta
CSE
2009
IEEE
16 years 1 months ago
Feedback Loops of Attention in Peer Production
—A significant percentage of online content is now published and consumed via the mechanism of crowdsourcing. While any user can contribute to these forums, a disproportionately...
Fang Wu, Dennis M. Wilkinson, Bernardo A. Huberman