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» Mechanisms for store-wait-free multiprocessors
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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 10 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
15 years 10 months ago
On the value locality of store instructions
Value locality, a recently discovered program attribute that describes the likelihood of the recurrence of previously-seen program values, has been studied enthusiastically in the...
Kevin M. Lepak, Mikko H. Lipasti
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
15 years 10 months ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
ICDCS
1995
IEEE
15 years 9 months ago
Parallel Processing on Networks of Workstations: A Fault-Tolerant, High Performance Approach
One of the mostsoughtaftersoftware innovation of thisdecade is the construction of systems using off-the-shelf workstations that actually deliver, and even surpass, the power and ...
Partha Dasgupta, Zvi M. Kedem, Michael O. Rabin
ARC
2010
Springer
186views Hardware» more  ARC 2010»
15 years 9 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan