206 search results - page 20 / 42 » Mechanisms for store-wait-free multiprocessors |
162
click to vote
IEEEPACT
2008
IEEE
16 years 15 days ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
203
click to vote
DSN
2011
IEEE
14 years 5 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
158
click to vote
HPCA
2001
IEEE
16 years 6 months ago
2001
IEEE
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
162
Voted
HIPEAC
2010
Springer
16 years 3 months ago
2010
Springer
As CMOS feature sizes venture deep into the nanometer regime, wearout mechanisms including negative-bias temperature instability and timedependent dielectric breakdown can severely...
162
click to vote
IEEEPACT
2008
IEEE
16 years 15 days ago
2008
IEEE
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...