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DAC
2001
ACM
16 years 7 months ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
VLSID
2006
IEEE
119views VLSI» more  VLSID 2006»
16 years 7 months ago
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core
Performance of applications can be boosted by executing application-specific Instruction Set Extensions (ISEs) on a specialized hardware coupled with a processor core. Many commer...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
16 years 1 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
IPPS
2006
IEEE
16 years 22 days ago
Parallelization and performance characterization of protein 3D structure prediction of Rosetta
The prediction of protein 3D structure has become a hot research area in the post-genome era, through which people can understand a protein’s function in health and disease, exp...
Wenlong Li, Tao Wang, Eric Li, D. Baker, Li Jin, S...
ISPAN
2005
IEEE
16 years 8 days ago
A Scalable Method for Predicting Network Performance in Heterogeneous Clusters
An important requirement for the effective scheduling of parallel applications on large heterogeneous clusters is a current view of system resource availability. Maintaining such ...
Dimitrios Katramatos, Steve J. Chapin