Sciweavers

4396 search results - page 601 / 880
» Measuring the Architecture Design Process
Sort
View
FPGA
2003
ACM
116views FPGA» more  FPGA 2003»
15 years 12 months ago
Hardware-assisted simulated annealing with application for fast FPGA placement
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
Michael G. Wrighton, André DeHon
CEC
2007
IEEE
15 years 8 months ago
Fitness inheritance in evolutionary and multi-objective high-level synthesis
Abstract—The high-level synthesis process allows the automatic design and implementation of digital circuits starting from a behavioral description. Evolutionary algorithms are v...
Christian Pilato, Gianluca Palermo, Antonino Tumeo...
SERP
2003
15 years 8 months ago
Reliability Modeling Using UML
System reliability has become an increasingly important benchmark in measuring service continuity. As part of many service level agreements, system performance is gauged by how lo...
Chokchai Leangsuksun, Hertong Song, Lixin Shen
BIOSYSTEMS
2007
52views more  BIOSYSTEMS 2007»
15 years 6 months ago
The genotypic complexity of evolved fault-tolerant and noise-robust circuits
Noise and component failure is an increasingly difficult problem in modern electronic design. Bioinspired techniques is one approach that is applied in an effort to solve such is...
Morten Hartmann, Pauline C. Haddow, Per Kristian L...
JCP
2008
126views more  JCP 2008»
15 years 6 months ago
Hardware/Software Co-design Approach for an ADALINE Based Adaptive Control System
Abstract--In this paper, we report some results on hardware and software co-design of an adaptive linear neuron (ADALINE) based control system. A discrete-time Proportional-Integra...
Shouling He, Xuping Xu