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» Measuring the Architecture Design Process
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DAC
2005
ACM
16 years 7 months ago
Exploiting suspected redundancy without proving it
We present several improvements to general-purpose sequential redundancy removal. First, we propose using a robust variety of synergistic transformation and verification algorithm...
Hari Mony, Jason Baumgartner, Viresh Paruthi, Robe...
DAC
2006
ACM
16 years 7 months ago
Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs
Multimedia applications usually have throughput constraints. An implementation must meet these constraints, while it minimizes resource usage and energy consumption. The compute i...
Sander Stuijk, Marc Geilen, Twan Basten
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 7 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
VLSID
2004
IEEE
142views VLSI» more  VLSID 2004»
16 years 7 months ago
Dynamic Noise Margin: Definitions and Model
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
Li Ding 0002, Pinaki Mazumder
183
Voted
HPCA
2004
IEEE
16 years 7 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...