4396 search results - page 583 / 880 » Measuring the Architecture Design Process |
155
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FPL
2003
Springer
16 years 3 hour ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
165
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
149
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GECCO
2006
Springer
15 years 10 months ago
2006
Springer
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
171
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CCGRID
2001
IEEE
15 years 10 months ago
2001
IEEE
The Globus Data Grid architecture provides a scalable infrastructure for the management of storage resources and data that are distributed across Grid environments. These services...
161
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DATE
2010
IEEE
15 years 9 months ago
2010
IEEE
An increasing concern amongst designers and integrators of military and defense-related systems is the underlying security of the individual microprocessor components that make up ...