Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghul...
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
We present an approach of how to automatically extract an XML document structure from a conceptual data model that describes the content of the document. We use UML class diagrams ...
Abstract—The use of local processing to reduce data transmission rates, and thereby power and bandwidth requirements, is common in wireless sensor networks. Achieving the minimum...
Abstract— Design trade-offs between estimation performance, processing delay and communication cost for a sensor scheduling problem is discussed. We consider a heterogeneous sens...
Henrik Sandberg, Maben Rabi, Mikael Skoglund, Karl...