4396 search results - page 516 / 880 » Measuring the Architecture Design Process |
163
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ATS
2004
IEEE
15 years 10 months ago
2004
IEEE
An efficient design for test methodology to increase the test yield of analog circuits is presented. It is assumed that the analog circuits are tested using alternate tests that r...
174
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RTAS
2000
IEEE
15 years 10 months ago
2000
IEEE
Policing of incoming packets can produce very high load in worst-case situations on a receiving computer. In realtime systems, resources must be allocated for such worstcase situa...
152
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ESSCIRC
2011
14 years 6 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
203
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PETRA
2009
ACM
16 years 1 months ago
2009
ACM
We propose a system to identify people in a sensor network. The system fuses motion information measured from wearable accelerometer nodes with motion traces of each person detect...
192
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SRDS
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper, we propose a novel ReliAble ProbabIlistic Dissemination protocol, RAPID, for mobile wireless ad-hoc networks that tolerates message omissions, node crashes, and sel...