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» Measuring the Architecture Design Process
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164
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DATE
2008
IEEE
129views Hardware» more  DATE 2008»
16 years 1 months ago
Memory Technology for Extended Large-Scale Integration in Future Electronics Applications
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
Dinesh Pamunuwa
197
Voted
CODES
2002
IEEE
15 years 12 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
187
Voted
KBSE
2010
IEEE
15 years 5 months ago
RESISTing reliability degradation through proactive reconfiguration
Situated software systems are an emerging class of systems that are predominantly pervasive, embedded, and mobile. They are marked with a high degree of unpredictability and dynam...
Deshan Cooray, Sam Malek, Roshanak Roshandel, Davi...
188
Voted
IPPS
2010
IEEE
15 years 4 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
IJCAI
2007
15 years 8 months ago
A Hybrid Ontology Directed Feedback Selection Algorithm for Supporting Creative Problem Solving Dialogues
We evaluate a new hybrid language processing approach designed for interactive applications that maintain an interaction with users over multiple turns. Specifically, we describe ...
Hao-Chuan Wang, Rohit Kumar, Carolyn Penstein Ros&...