Sciweavers

4396 search results - page 423 / 880
» Measuring the Architecture Design Process
Sort
View
ASYNC
1999
IEEE
136views Hardware» more  ASYNC 1999»
15 years 11 months ago
A Counterflow Pipeline Experiment
The counterflow pipeline architecture [12] consists of two interacting pipelines in which data items flow in opposite directions. Interactions occur between two items when they me...
Bill Coates, Jo C. Ebergen, Jon K. Lexau, Scott Fa...
HT
2009
ACM
15 years 10 months ago
Dynamic hypertext generation for reusing open corpus content
Adaptive hypermedia systems traditionally focus on providing personalised learning services for formal or informal learners. The learning material is typically sourced from a prop...
Ben Steichen, Séamus Lawless, Alexander O'C...
CIDR
2011
252views Algorithms» more  CIDR 2011»
14 years 10 months ago
Hyder - A Transactional Record Manager for Shared Flash
Hyder supports reads and writes on indexed records within classical multi-step transactions. It is designed to run on a cluster of servers that have shared access to a large pool ...
Philip A. Bernstein, Colin W. Reid, Sudipto Das
DAC
2011
ACM
14 years 6 months ago
Process-level virtualization for runtime adaptation of embedded software
Modern processor architectures call for software that is highly tuned to an unpredictable operating environment. Processlevel virtualization systems allow existing software to ada...
Kim M. Hazelwood
DAC
2004
ACM
16 years 7 months ago
Selective gate-length biasing for cost-effective runtime leakage control
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Denn...