Abstract— The translation of user requirements to system constraints and parameters during an exploration exercise is a hard problem, especially in the context of large scale emb...
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
After a reminder about embryonic machines endowed with universal construction and universal computation properties, this paper presents a novel architecture providing additional s...
Power consumption and portability issues are becoming increasingly significant in embedded system architectures. Therefore, it is important that chip architects and integrated circ...
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...