4396 search results - page 391 / 880 » Measuring the Architecture Design Process |
153
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DAC
2003
ACM
16 years 1 days ago
2003
ACM
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) so...
252
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
As the d esig n-m anu factu ring interface becom es increasing ly com plicated with IC technolog y scaling , the correspond ing process variability poses g reat challeng es for na...
202
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IPPS
2010
IEEE
15 years 4 months ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
191
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TC
2010
15 years 5 months ago
2010
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
193
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PVM
1997
Springer
15 years 11 months ago
1997
Springer
We present Ensemble, a message-passing implementation methodology, applied to PVM. Ensemble overcomes problems and complexities in developing applications in messagepassing enviro...