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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 24 days ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
221
Voted
PVM
2010
Springer
15 years 5 months ago
Toward Performance Models of MPI Implementations for Understanding Application Scaling Issues
Abstract. Designing and tuning parallel applications with MPI, particularly at large scale, requires understanding the performance implications of different choices of algorithms ...
Torsten Hoefler, William Gropp, Rajeev Thakur, Jes...
204
Voted
CASES
2005
ACM
15 years 8 months ago
Exploring the design space of LUT-based transparent accelerators
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
167
Voted
SIPS
2008
IEEE
16 years 1 months ago
Low-complexity high-speed 4-D TCM decoder
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture f...
Jinjin He, Zhongfeng Wang, Huaping Liu
TREC
2001
15 years 8 months ago
Multilingual Question/Answering: the DIOGENE System
This paper presents the DIOGENE question/answering system developed at ITCIrst. The system is based on a rather standard architecture which includes three components for question ...
Bernardo Magnini, Matteo Negri, Roberto Prevete, H...