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ICASSP
2011
IEEE
14 years 10 months ago
Joint algorithm-architecture optimization of CABAC to increase speed and reduce area cost
To address the increasing demand for higher resolution and frame rates, processing speed (i.e. performance) and area cost need to be considered in the development of next generati...
Vivienne Sze, Anantha P. Chandrakasan
DAC
2000
ACM
16 years 7 months ago
An architecture-driven metric for simultaneous placement and global routing for FPGAs
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
Yao-Wen Chang, Yu-Tsang Chang
DAC
2005
ACM
15 years 8 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
DAC
2010
ACM
15 years 7 months ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
VRML
2010
ACM
15 years 10 months ago
Cognitive scaffolding in Web3D learning systems: a case study for form and structure
In this paper, we describe a case study in usability engineering for Web3D learning systems and introduce a new step to the typical methods of the usability design. Pedagogical ap...
Felipe Bacim, Nicholas F. Polys, Jian Chen, Mehdi ...