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SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
PERCOM
2003
ACM
15 years 12 months ago
An Architecture that Treats Everyday Objects as Communicating Tangible Components
The paper describes research that has been carried out in “extrovert-Gadgets”, a research project funded in the context of EU IST/FET proactive initiative “Disappearing Comp...
Achilles Kameas, Stephen J. Bellis, Irene Mavromma...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 3 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
AAAI
2010
15 years 8 months ago
Facilitating the Evaluation of Automated Negotiators using Peer Designed Agents
Computer agents are increasingly deployed in settings in which they make decisions with people, such as electronic commerce, collaborative interfaces, and cognitive assistants. Ho...
Raz Lin, Sarit Kraus, Yinon Oshrat, Ya'akov (Kobi)...
ACSAC
1998
IEEE
15 years 11 months ago
An Architecture for Intrusion Detection Using Autonomous Agents
The Intrusion Detection System architectures commonly used in commercial and research systems have a number of problems that limit their configurability, scalability or efficiency...
J. S. Balasubramaniyan, J. O. Garcia-Fernandez, D....