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IPPS
2007
IEEE
16 years 26 days ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
MOBIS
2008
15 years 8 months ago
Business Process Compliance Checking: Current State and Future Challenges
Abstract: Regulatory compliance sets new requirements for business process management (BPM). Companies seek to enhance their corporate governance processes and are required to put ...
Marwane El Kharbili, Ana Karla A. de Medeiros, Seb...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
16 years 3 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
15 years 10 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose
EUROSYS
2007
ACM
16 years 3 months ago
Sprint: a middleware for high-performance transaction processing
Sprint is a middleware infrastructure for high performance and high availability data management. It extends the functionality of a standalone in-memory database (IMDB) server to ...
Lásaro J. Camargos, Fernando Pedone, Marcin...