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» Measuring the Architecture Design Process
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DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 12 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
MM
2005
ACM
103views Multimedia» more  MM 2005»
16 years 3 days ago
IrisNet: an internet-scale architecture for multimedia sensors
Most current sensor network research explores the use of extremely simple sensors on small devices called motes and focuses on overcoming the resource constraints of these devices...
Jason Campbell, Phillip B. Gibbons, Suman Nath, Pa...
ISCAPDCS
2007
15 years 8 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
DSN
2007
IEEE
16 years 27 days ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
BIS
2010
185views Business» more  BIS 2010»
15 years 4 months ago
From Economic Drivers to B2B Process Models: A Mapping from REA to UMM
Inter-organizational B2B systems are most likely tending to change their business requirements over time - e.g. establishing new partnerships or change existing ones. The problem i...
Rainer Schuster, Thomas Motal, Christian Huemer, H...